kqcircuits.util.netlist_extraction.export_cell_netlist(cell, filename, pcell=None, alt_netlists=None)[source]

Exports netlist(s) in JSON into file(s).

The file will have four sections: {"nets": {...}, "subcircuits": {...}, "circuits": {...}, "chip": {...}}

KLayout’s terminology differs from the one used in typical EDA tools where we have components (resistors, capacitors, etc.), pins (the endpoints of components) and nets (i.e. wires between pins). Components are PCell instances, a.k.a. cells, these are called subcircuits in the netlist file.

The main conceptual difference is that waveguides, that would be analogous to wires, are also treated as components. Consequently, a net in the nets section usually contains exactly two overlapping pins that belong to two different components each identified by a unique subcircuit_id. One of these is almost always a waveguide. Unconnected pins are not shown except for Launchers.

The subcircuits section is a dictionary of the used cells: <subcircuit_id>: {"cell_name": "...", "subcircuit_location": {"_pya_type": "DPoint", "x": <x>, "y": <y>}, ...}. Where cell_name is the name of the used Element optionally appended with $<n> if there are more than one Elements of the same type. Different instances of the same cell will have different subcircuit_id but identical cell_name. subcircuit_location defines the center of the bounding box of the subcircuit’s geometry in base_metal_gap_wo_grid layer, while subcircuit_origin defines the center of the bounding box of netlist ports of the cell.

The circuits section maps cell_name to a dictionary of the named Element’s parameters.

If the Cell object is a Chip, the chip section contains bounding boxes of each face in the chip.

This function may generate alternative netlists too as specified in the alt_netlists dictionary. The keys should be tags that get added to the generated netlist filenames and the values are the corresponding Element breakdown lists used to generate them. The default netlist is generated regadless of this parameter.

  • cell – pya Cell object

  • filename – absolute path as convertible to string

  • pcell – pya PCell object. If None, an attempt is made to treat cell as pcell

  • alt_netlists – optional dictionary of file name postfixes and element breakdown lists


Extract dictionary for net for JSON export

kqcircuits.util.netlist_extraction.extract_circuits(cell_mapping, internal_cell, layout)[source]

Extract dictionary for circuit for JSON export