Source code for kqcircuits.simulations.single_xmons_full_chip_sim

# This code is part of KQCircuits
# Copyright (C) 2021 IQM Finland Oy
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from kqcircuits.chips.single_xmons import SingleXmons
from kqcircuits.pya_resolver import pya
from kqcircuits.simulations.port import EdgePort, InternalPort
from kqcircuits.simulations.simulation import Simulation
from kqcircuits.util.parameters import Param, pdt
from kqcircuits.defaults import default_junction_test_pads_type


[docs] class SingleXmonsFullChipSim(Simulation): n: int launchers: bool use_test_resonators: bool launchers = Param(pdt.TypeBoolean, "True to include launchers in simulation", False) use_test_resonators = Param(pdt.TypeBoolean, "True to include XS1-type test resonators. False produces XS2", False)
[docs] def build(self): mask_parameters_for_chip = { "name_mask": self.name, "name_copy": None, "with_grid": False, } chip = self.add_element( SingleXmons, **{ **mask_parameters_for_chip, "name_chip": "XS1" if self.use_test_resonators else "XS2", "readout_res_lengths": [4490.35, 4578.13, 4668.99, 4763.09, 4860.61, 4961.75], "use_test_resonators": self.use_test_resonators, "test_res_lengths": [4884.33, 4804.94, 4728.06, 4653.58], "n_fingers": 4 * [4], "l_fingers": [23.65, 24.204, 24.7634, 25.325], "type_coupler": 4 * ["plate"], "junction_type": "Sim", "n": self.n, }, ) # Remove unneeded elements self.delete_instances(chip, "Chip Frame") self.delete_instances(chip, default_junction_test_pads_type, range(2)) # Insert chip and get refpoints _, refpoints = self.insert_cell(chip, rec_levels=None) if not self.launchers: # Remove launchers self.delete_instances(chip, "Launcher") maximum_box = pya.DBox(pya.DPoint(800, 800), pya.DPoint(9200, 9200)) port_shift = 0 else: maximum_box = pya.DBox(pya.DPoint(200, 200), pya.DPoint(9800, 9800)) port_shift = 600 # Limit the size of the box to fit the ports self.box &= maximum_box # Define edge ports, shifted inward by port_shift w.r.t. launcher refpoints for i, (launcher, shift) in enumerate( zip( ["NW", "WN", "WS", "SW", "SE", "ES", "EN", "NE"], [ [0, port_shift], [-port_shift, 0], [-port_shift, 0], [0, -port_shift], [0, -port_shift], [port_shift, 0], [port_shift, 0], [0, port_shift], ], ) ): self.ports.append(EdgePort(i + 1, refpoints[f"{launcher}_port"] + pya.DVector(*shift))) # Add squid internal ports for j in range(6): self.ports.append( InternalPort( j + 9, *self.etched_line(refpoints[f"qb_{j}_port_squid_a"], refpoints[f"qb_{j}_port_squid_b"]), ) )